1. Field of the Invention
This invention relates to integrated circuit structures and methods of fabricating them, and to a technique for fabricating integrated circuit structures utilizing replicating coatings and lateral etching techniques to reliably define smaller features in integrated circuit structures than heretofore possible. The invention also relates to integrated circuit structures fabricated utilizing such techniques.
2. Description of the Prior Art
Integrated circuit fabrication technology utilizing lateral etching processes is known. For example, in U.S. Pat. No. 3,940,288, M. Takati et al. teach several techniques for fabricating transistors and associated electrical connections. Some of these techniques utilize lateral etching and double diffusion technology to fabricate transistor structures. M. Paffen et al. in U.S. Pat. No. 3,783,047, teach the fabrication of different integrated circuit structures which may be fabricated utilizing lateral etching techniques.
H. Kamioka et al. in "A New Sub-Micron Emitter Formation with Reduced Base Resistance for Ultra High Speed Devices," presented in December 1974 to the International Electron Devices Meeting, and published at page 279 of the Technical Digest of that meeting teach the fabrication of a compact NPN vertical transistor. The structure shown therein utilizes lateral etching techniques to define the emitter region. W. Hunter in "New Edge-Defined Vertical-Etch Approaches for Sub-micrometer MOSFET Fabrication" presented at the 1980 International Electron Devices Meeting and described beginning on page 764 of the Technical Digest of that meeting teaches the fabrication of regions in MOS devices utilizing lateral etching techniques and conformal coatings.